Method and apparatus for designing an integrated circuit

ABSTRACT

Method and apparatus for designing an integrated circuit by providing an IC layout design. Adding one or more assist features to the IC layout design. Identifying which of the one or more added assist features in the IC layout design will cause one or more defects in the resultant wafer die manufactured from the IC layout design. Amending the one or more identified assist features.

FIELD OF THE INVENTION

The present invention relates to a method and apparatus for designing anintegrated circuit.

BACKGROUND OF THE INVENTION

When making an integrated circuit (which may also be referred to as anIC, chip or device), a design layout of the IC is made using, forexample, CAD tools. A reticle or mask is then produced for the IC designlayout and then photolithography is used to transfer features from thereticle or mask to a die (integrated circuit semiconductor wafer).

Various techniques are used to reduce the level of defects in theresultant die. For instance, prior to the production of the reticle, thedesign layout may be optimised using optical proximity correction (OPC)to create a reticle layout. This optimisation process amends thephysical design layout in order to avoid optical or process distortionsalso known as patterning defects when features are transferred from thereticle or mask that may cause failures of the device.

Assist features may be added to an IC layout design to reduce opticaldistortions. Preferably, assist features should not be printed on theresultant die and so usually assist features are small when compared tothe required feature of an IC layout design.

Furthermore, a cautionary approach to assist features is usually takenwith fewer being included in an IC layout design rather than risking theprinting of the assist features on the resultant wafer die. Althoughthis cautionary approach leads to fewer assist features being printed onthe reticle or mask other defects may remain uncorrected that may havebenefited from one or more additional assist features.

SUMMARY OF THE INVENTION

The present invention provides a method and apparatus for designing anintegrated circuit as described in the accompanying claims.

BRIEF DESCRIPTION OF THE FIGURES

The present invention may be put into practice in a number of ways andan embodiment will now be described by way of example only and withreference to the accompanying drawings, in which:

FIG. 1 shows a SEM image of a portion of a wafer die including a defect;

FIG. 2 shows a schematic diagram of a portion of an IC layout designcorresponding to the area shown in FIG. 1;

FIG. 3 shows a schematic diagram of a feature within an IC layout designincluding an assist feature;

FIG. 4 shows schematic diagram of the feature of FIG. 3 with an amendedassist feature; and

FIG. 5 shows a flowchart of a method for designing an integrated circuitaccording to an embodiment of the present invention, given by way ofexample.

It should be noted that the figures are illustrated for simplicity andare not necessarily drawn to scale.

DETAILED DESCRIPTION OF AN EMBODIMENT

FIGS. 1 and 2 shall now be used to illustrate how one example opticaldefect develops and how assist features may be used to avoid these typesof defects.

FIG. 1 shows an SEM of a portion of a wafer die 10. The wafer die wasmanufactured with the reticle deliberately defocused to cause a defect.Features 30 are formed on substrate 20 of the wafer die 10 and representfeatures of an IC. Circle 40 highlights an area on the wafer die 10containing a defect. This defect results in a break in one track and ashort circuit to another track.

FIG. 2 shows a schematic diagram of an IC layout design 10′corresponding to the area shown in FIG. 1. Similar features have beengiven the same reference numerals.

Assist features 60 are shown within the IC layout design 10′. Circle 40′highlights an area on the IC layout design 10′ that does not contain anassist feature and which therefore led to the defect in FIG. 1. Theaddition of an assist feature within this circle 40′ should correct thedefect shown in FIG. 1 by changing the optical response of the reticleused to produce the wafer die.

FIGS. 1 and 2 highlight the importance of assist features in avoidingdefects caused by diffraction and other optical or etching effects.

Assist features may be applied to an IC layout design using a set ofrules. The more aggressive the rules, the more assist features areincluded leading to fewer optical or etching defects forming in theresultant die. However, with more aggressive rules a higher number ofassist features may be printed in the resultant wafer die. Printedassist features are themselves defects as they may lead to shortcircuits or to other electrical failures in the IC circuit.

FIGS. 3 and 4 shall now be used to describe how printed assist featuresmay be modified so that they no longer print.

FIG. 3 shows a schematic diagram of an example feature, a single gate100, within an IC layout design. Assist feature 120 is present to ensurethat the features of the gate 100 are formed correctly on a resultantwafer die. The length of assist feature 120 is indicated by arrow 130.An optical and/or resist optimisation or simulation technique may beused to check if assist feature 120 will be printed on a resultant waferdie. Should this optimisation or simulation predict that assist feature120 will be printed this assist feature may be modified in a number ofways in order to avoid or reduce the likelihood of such printing. It maybe a goal of the optimisation process to minimise such printed defects.The optimisation or simulation may be performed as part of an OPCprocess or separate to it (before or after).

FIG. 4 shows the same gate 100 as FIG. 3 but assist feature 120 has beenshortened as shown by arrow 130′. This shortening reduces theprobability of the assist feature 120 being printed.

Other amendments may be made to assist features to avoid them beingprinted and include moving the assist feature closer or further awayfrom the feature being corrected (in FIGS. 3 and 4 the feature is a gate100 but other features may be used) or reduced in size. Alternatively,the assist features found to be printed in simulation may be deletedfrom the IC layout design. Other amendments to assist features may alsobe used. The severity of the defect caused by a printed assist featuremay be assessed with higher severity defects being corrected by totalremoval of the offending assist feature and lower severity defectsleading to an amendment of the assist feature causing the defect.

FIG. 5 shows a flowchart of a method 210 for designing an IC accordingto one aspect of the present invention. Method 210 does not contain allof the steps for designing an IC and the remaining steps will befamiliar to the skilled person. The process starts with providing an IClayout design 220.

Next, assist features are added to the IC layout design 230. Assistfeatures may be added using a rule based technique or other scheme. Inparticular, the assist features may be added aggressively, such that aproportion may be printed should the IC layout design be manufactured atthis stage.

For instance, the size and shape of assist features may be limited byrules to prevent them from being printed. A more aggressive scheme mayallow larger, for instance, longer or wider, assist features to beintroduced. These larger assist features may be used to further improvethe depth of focus achievable by a reticle. However, a proportion ofthese larger (or otherwise shaped) assist features may be printed on aresultant wafer die or cause other defects to arise.

The next step is to identify which of the one or more added assistfeatures in the IC layout design will cause one or more defects in theresultant die manufactured from the IC layout design. In an embodimentof the invention, a coarse OPC process may be performed. Model or rulebased OPC software may be used such as that supplied by Mentor Graphics®of Wilsonville, Oreg. USA or Synopsys, Inc. of Mountain View, Calif.USA, for instance. The OPC process need not be coarse but this minimisesthe required computer run-time. In any case, a full OPC process and/orsimulation may not be required as the purpose of this step is toidentify which assist features will be printed. The location or otheridentifier of printed assist features may also be stored during thisstep.

A coarse OPC process may involve a limited number or type of rules in arule based process or a simple model in a model based simulation.

Next, the identified assist features (that may be printed) are modifiedor amended in step 250. Amendments may be made such that defect causingassist features no longer cause defects or reduces the likelihood orprobability of defects to occur in a resultant IC wafer die. Amendmentsmay be carried as described with reference to FIGS. 3 and 4 or otheradjustments to the IC layout design may be made in order to suppress theprinting of unwanted assist features or other defects. For instance,surrounding features may also be amended or moved.

Several iterations of steps 240 and 250 may occur until no furtherprinting assist features are identified or the number of suspectedassist features is reduced to an acceptable limit.

Next, a finer OPC process and/or simulation may be carried out as step260. This fine OPC process may be used to find any remaining printingassist features or other defects in the IC layout design. The resultantIC layout design may be used to manufacture an IC wafer die in accordingto the usual methods. The fine OPC process may involve more complex or ahigher number of rules than that of the coarse OPC process 240.

According to this method many more assist features may be added at step230 than would be possible without them being filtered from the designas described above. Initially more assist features are added to the IClayout design and then problematic or possibly defective assist featuresare filtered out leaving more reliable assist features. This methodtherefore reduces the likelihood of optical defects occurring withoutcausing assist features to be present in the final wafer die. In otherwords, a more aggressive set of rules may be used to place assistfeatures within the IC layout design than could be used in prior artmethods.

The method described above may be carried out in an automated mannerusing suitable apparatus or a computer programmed to perform each of themethod steps. Suitable computer systems include PCs running a Windows®operating system or a UNIX based system such as a SPARC system runningSolaris® by Sun Microsystems.

As will be appreciated by the skilled person, details of the aboveembodiment may be varied without departing from the scope of the presentinvention, as defined by the appended claims.

For example, identified assist features may be marked instead of or aswell as being amended or deleted.

Step 240 uses a coarse OPC process to identify the printed assistfeatures. However, other techniques may be used to identify or filterout these features.

Steps 240 and 250 may be combined so that the OPC process and/orsimulation includes an optimisation process to amend any printed assistfeatures to reduce the probability of them being printed on theresultant wafer die.

The coarse OPC step 240 may be model or rule based OPC.

Steps 240 and 250 may be iterated until a predetermined number,percentage or density of defects is reached rather than eliminating alldefects such as printed assist features. This avoids an infinite loopshould persistent defects occur.

1. A method for designing an integrated circuit, IC, comprising thesteps of: (a) providing an IC layout design; and (b) adding one or moreassist features to the IC layout design; (c) identifying which of theone or more added assist features in the IC layout design will cause oneor more defects in the resultant wafer die manufactured from the IClayout design; and (d) amending the one or more assist featuresidentified in step (c); and (e) identifying any remaining defects usinga fine OPC process, wherein the coarse OPC process comprises fewer rulesor a simpler model than the fine OPC process.
 2. (canceled) 3.(canceled)
 4. The method according to claim 1, wherein step (c) furthercomprises simulating the IC layout design.
 5. The method according toclaim 2, wherein the simulation is an optical and/or resist simulation.6. The method according to claim 1, wherein the one or more defects is aprinted assist feature.
 7. The method according to claim 1, wherein step(c) further comprises storing the location or locations of theidentified one or more assist features.
 8. The method according to claim1, wherein step (c) further comprises identifying a neighbouring featureof the IC layout design to the identified one or more assist features.9. The method according to claim 1, wherein step (d) further comprisesmoving an edge of the one or more identified assist features.
 10. Themethod according to claim 1, wherein step (d) further comprisesshortening the one or more identified assist features.
 11. The methodaccording to claim 1, wherein step (d) further comprises moving the oneor more identified assist features.
 12. The method according to claim 1,wherein step (d) further comprises deleting the one or more identifiedassist features.
 13. The method according to claim 1, wherein step (b)further comprises adding assist features to the IC layout design suchthat one or more of the added assist features will cause a defect to besubsequently identified in step (c).
 14. The method according to claim1, wherein step (b) is performed to improve the depth of focus of the IClayout design.
 15. The method according to claim 1, wherein the one ormore assist features added in step (b) are added using a design rule.16. The method according to claim 13, wherein the design rule allows aspecific proportion of assist features to be printed on a resultantwafer die.
 17. The method according to claim 1, wherein step (d) isperformed such that the probability is reduced of the occurrence of theone or more defects in the resultant wafer die.
 18. The method accordingto claim 1, wherein step (d) is performed such that the one or moredefects is removed.
 19. (canceled)
 20. (canceled)
 21. (canceled)
 22. Anintegrated circuit manufactured according to the method comprising thesteps of: (a) providing an IC layout design; (b) adding one or moreassist features to the IC layout design; (c) identifying which of theone or more added assist features in the IC layout design will cause oneor more defects in the resultant wafer die manufactured from the IClayout design; (d) amending the one or more assist features identifiedin step (c); and (e) identifying any remaining defects using a fine OPCprocess, wherein the coarse OPC process comprises fewer rules or asimpler model than the fine OPC process.
 23. Apparatus for designing anintegrated circuit comprising: means for providing an IC layout design;and means for adding one or more assist features to the IC layoutdesign; means for identifying which of the one or more added assistfeatures in the IC layout design will cause one or more defects in theresultant wafer die manufactured from the IC layout design using acoarse optical proximity correction, OPC, process; means for amendingthe one or more identified assist features; and means for identifyingany remaining defects using a fine OPC process, wherein the coarse OPCprocess comprises fewer rules or a simpler model than the fine OPCprocess.
 24. The integrated circuit according to claim 22, wherein theone or more defects is a printed assist feature.